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1. general description the pcf2127a is a cmos 1 real time clock (rtc) and calendar with an integrated temperature compens ated crystal (xtal) oscillator (tcxo) and a 32 .768 khz quartz crystal optimized for very high accuracy and very low power consumption. the pcf2127a has 512 bytes of general purpose static ram, a selectable i 2 c-bus or spi-bus, a backup battery switch-over circuit, a programmable wa tchdog function, a timestamp function, and many other features. 2. features and benefits ? temperature comp ensated crystal oscillator (tcx o) with integrated capacitors ? typical accuracy: 3ppm from ? 15 c to +60 c ? integration of a 32.768 khz quartz crys tal and oscillator in the same package ? provides year, month, day, weekda y, hours, minutes, and seconds ? 512 bytes of general purpose static ram ? timestamp function ? with interrupt capability ? detection of two different events on one multilevel input pin (e.g. for tamper detection) ? two line bidirectional 400 khz fast-mode i 2 c-bus interface (i ol = 3 ma at pin sda/ce ) ? 3 line spi-bus with separate data input and output (maximum speed 6.5 mbit/s) ? battery backup input pin and switch-over circuitry ? battery backed output voltage pin ? battery low detection function ? extra power fail detection function with input and output pins ? power-on reset override (poro) ? oscillator stop detection function ? interrupt output and system reset pin (open-drain) ? programmable 1 second or 1 minute interrupt ? programmable countdown timer with interrupt capability ? programmable watc hdog timer with interrupt and reset capability ? programmable alarm function with interrupt capability ? programmable square wave open-drain output pin ? clock operating voltage: 1.2 v to 4.2 v ? low supply current: typical 0.65 a at v dd = 3.0 v and t amb =25 c pcf2127a integrated rtc, tcxo and quartz crystal rev. 02 ? 7 may 2010 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 17 .
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 2 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal ? automatic leap year correction 3. applications ? electronic metering for el ectricity, water, and gas ? timekeeping instruments with high precision ? gps equipment to reduce time to first fix ? applications that require an accurate process timing ? products with long automated unattended operation time 4. ordering information 5. marking table 1. ordering information type number package name description version PCF2127AT/1 so20 plastic small outline pack age; 20 leads; body width 7.5 mm sot163-1 table 2. marking codes type number marking code PCF2127AT/1 PCF2127AT
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 3 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 6. block diagram fig 1. block diagram of pcf2127a 001aaj67 5 test pfo scl scl sdo temp 1.25 v (internal) sdi v dd bbs v bat v ss internal power supply rst sdi sdo clkout int osci osco temp 1 hz 32.768 khz tcxo battery back up switch-over circuitry oscillator monitor serial bus interface selector spi-bus interface i 2 c-bus interface 512 bytes static ram temperature sensor reset logic control divider and timer address register control_1 control_2 control_3 00h 01h 02h seconds 03h minutes 04h hours 05h days 06h weekdays 07h months 08h years 09h second_alarm 0ah minute_alarm 0bh hour_alarm 0ch day_alarm 0dh weekday_alarm 0eh clkout_ctl 0fh watchdg_tim_ctl 10h watchdg_tim_val 11h timestp_ctl 12h sec_timestp 13h min_timestp 14h hour_timestp 15h day_timestp 16h mon_timestp 17h year_timestp 18h aging_offset 19h ram_addr_msb 1ah ram_addr_lsb 1bh ram_wrt_cmd 1ch ram_rd_cmd 1dh sda/ce ifs pfi ts sda/ce pcf2127a r pu
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 4 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 7. pinning information 7.1 pinning 7.2 pin description top view. for mechanical details, see figure 53 . fig 2. pin configuration for so20 (pcf2127a) pcf2127a scl v dd sdi v bat sdo bbs sda/ce int ifs rst ts pfi clkout pfo v ss test n.c. n.c. n.c. n.c. 001aaj676 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 table 3. pin description of so20 (pcf2127a) symbol pin description scl 1 combined serial clock input for both i 2 c-bus and spi-bus; may float when sda/ce inactive sdi 2 serial data input for spi-bus; may float when sda/ce inactive sdo 3 serial data output for spi-bus, push-pull sda/ce 4 combined serial data input and output for the i 2 c interface and chip enable input (active low) for the spi-bus ifs 5 interface selector input connect to pin v ss to select the spi-bus connect to pin bbs to select the i 2 c interface ts 6 timestamp input (active low) with 200 k internal pull-up resistor (r pu ) clkout 7 clock output (open-drain) v ss 8 ground supply voltage n.c. 9 to 12 not connected; do not c onnect; do not use as feed through test 13 do not connect; do not use as feed through pfo 14 power fail output (open-drain; active low) pfi 15 power fail input rst 16 reset output (open-drain; active low) int 17 interrupt output (open-drain; active low) bbs 18 output voltage (battery backed) v bat 19 battery supply voltage (backup) v dd 20 supply voltage
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 5 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8. functional description the pcf2127a is a real time clock (rtc) and calendar with an on-chip temperature compensated crystal (xtal) oscillator (tcxo) and a 32.768 khz quar tz crystal integrated into the same package. address and data are transferred by a selectable 400 khz fast-mode i 2 c-bus or a 3 line spi-bus with separate data input and output (see section 9 ). the maximum speed of the spi-bus is 6.5 mbit/s. the pcf2127a contains 30 8-bit registers that are used for many different functions, such as clock, alarm, watchdog, timer, timestamp etc. (see section 8.1 ). the pcf2127a has an output reset pin: the output reset is activated on power-on reset (por), and whenever the oscillator is stopped (see section 8.8 ). the pcf2127a features 512 bytes of general purpose static ram, which is battery backed and can be used independently of the rtc functionality (see section 8.5 ). the pcf2127a has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply and au tomatically switches to the backup battery when a power failure condition is detected (see section 8.6.1 ). accurate timekeeping is maintained even when the main power supply is interrupted. a battery low detection circuit monito rs the status of the battery (see section 8.6.3 ). when the battery voltage goes below a certain threshold value, a flag is set to indicate that the battery must be replaced. this can be used to ensure the integrity of the data during periods of battery backup. a power failure detection circuit monitors the voltage of the power fail input pin pfi. when the voltage on the power fail input pin pfi goes below an internal reference (1.25 v), the power fail output pin pfo is activated (see section 8.6.4 ).
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 6 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.1 register overview the pcf2127a contains 30 8-bit registers (see ta b l e 4 ) with an auto-incrementing address register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1b h. after register 1bh the auto-incrementing will wrap around to address 00h. the registers 1ch and 1dh must be addressed directly (see figure 3 ). ? the first three registers (memory address 00h, 01h, and 02h) are used as control registers (see section 8.2 ). ? the memory addresses 03h through to 09h are used as counters for the clock function (seconds up to years). the date is automatically adju sted for months with fewer than 31 days, including corrections for leap years. the clock can operate in 12-hour mode with an am/pm indication or in 24-hour mode (see section 8.9 ). ? addresses 0ah through 0eh define the alarm function. it can be selected that an interrupt is generated when an alarm event occurs (see section 8.10 ). ? the register 0fh defines the temperature measurement period and the clock out mode. the temperature measurement can be selected from every 4 minutes (default) down to every 30 seconds (see ta b l e 9 ). clkout frequencies of 32.768 khz (default) down to 1 hz for use as a system clock, a microcontroller clock etc. can be chosen (see ta b l e 1 0 ). ? address registers 10h and 11h are used for the watchdog and countdown timer functions. the timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours (see table 36 ). either the watchdog timer or the countdown timer can be enabled (see section 8.11 ). for the watchdog timer it is possible to select whether an inte rrupt or a pulse on the reset pin will be generated when the watchdog times out. for the countdown timer it is only possible that an interrupt will be gener ated at the end of the countdown. ? address registers 12h to 18h are used for the timestamp function. when the trigger-event happens the actual time is saved in the timestamp registers (see section 8.12 ). ? address register 19h is used for the correction of the crystal aging effect (see section 8.4.1 ). fig 3. handling address registers 001aaj30 7 address register 00h auto-increment wrap around 01h 02h 03h ... 19h 1ah 1bh 1ch 1dh not reachable by auto-inc. - needs to be addressed directly not reachable by auto-inc. - needs to be addressed directly
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 7 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal ? address registers 1ah and 1bh define th e ram address. address register 1ch (ram_wrt_cmd) is the ram write command; address register 1dh (ram_rd_cmd) is the ram read command. data is transferred to or from the ram via the serial interface (see section 8.5 ). ? the registers seconds, minu tes, hours, days, months, and years are all coded in binary coded decimal (bcd) format to simp lify application use. other registers are either bit-wise or standard binary. when one of the rtc registers is written or r ead, the content of all counters is temporarily frozen. this prevents a faulty writing or reading of the clock and calendar during a carry condition (see section 8.9.8 ). table 4. register overview bit positions labeled as - are not implemented and will return a 0 when read. bit t must always be written with logic 0. bits labeled as x are undefined at power- on and unchanged by subsequent resets. address register name bit reset value 7 6 5 4 3 2 1 0 control registers 00h control_1 ext_ test tstoptsf1por_ ovrd 12_24 mi si 0000 0000 01h control_2 msf wdtf tsf2 af cdtf tsie aie cdtie 0000 0000 02h control_3 pwrmng[2:0] btse bf blf bie blie 0000 0000 time and date registers 03h seconds osf seconds (0 to 59) 1xxx xxxx 04h minutes - minutes (0 to 59) - xxx xxxx 05h hours - - ampm hours (1 to 12) in 12 h mode - - xx xxxx hours (0 to 23) in 24 h mode - - xx xxxx 06h days - - days (1 to 31) - - xx xxxx 07hweekdays----- w eekdays (0 to 6) - - - - - xxx 08h months - - - months (1 to 12) - - - x xxxx 09h years years (0 to 99) xxxx xxxx alarm registers 0ah second_alarm ae_s second_ alarm (0 to 59) 1xxx xxxx 0bh minute_alarm ae_m minut e_alarm (0 to 59) 1xxx xxxx 0ch hour_alarm ae_h - ampm hour_alarm (1 to 12) in 12 h mode 1 - xx xxxx - hour_alarm (0 to 23) in 24 h mode 1 - xx xxxx 0dh day_alarm ae_d - day_alarm (1 to 31) 1 - xx xxxx 0ehweekday_alarmae_w----w eekday_alarm (0 to 6) 1 - - - - xxx clkout control register 0fhclkout_ctltcr[1:0] ---cof[2:0] 00---000 watchdog registers 10h watchdg_tim_ctl wd_cd[1:0] ti_tp - - - tf[1:0] 000 - - - 11 11h watchdg_tim_val watchdg_tim_val[7:0] xxxx xxxx timestamp registers 12h timestp_ctl tsm tsoff - 1_o_16_timestp[4:0] 00 - x xxxx 13h sec_timestp - second_timestp (0 to 59) - xxx xxxx
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 8 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 14h min_timestp - minute_timestp (0 to 59) - xxx xxxx 15h hour_timestp - - ampm hour_timestp (1 to 12) in 12 h mode - - xx xxxx hour_timestp (0 to 23) in 24 h mode - - xx xxxx 16h day_timestp - - day_timestp (1 to 31) - - xx xxxx 17hmon_timestp---month_timestp (1 to 12) ---x xxxx 18h year_timestp year_tim estp (0 to 99) xxxx xxxx aging offset register 19h aging_offset ----ao[3:0] ----1000 ram registers 1ahram_addr_msb-------ra8-------0 1bh ram_addr_lsb ra[7:0] 0000 0000 1chram_wrt_cmdxxxxxxxx xxxx xxxx 1dhram_rd_cmdxxxxxxxx xxxx xxxx table 4. register overview ?continued bit positions labeled as - are not implemented and will return a 0 when read. bit t must always be written with logic 0. bits labeled as x are undefined at power- on and unchanged by subsequent resets. address register name bit reset value 7 6 5 4 3 2 1 0
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 9 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.2 control registers pcf2127a has 30 8-bit registers. the first 3 registers with the addresses 00h, 01h, and 02h are used as control registers. 8.2.1 register control_1 [1] default value. [2] when writing to the register this bit has always to be set logic 0. table 5. control_1 - control and status re gister 1 (address 00h) bit description bit symbol value description reference 7 ext_test 0 [1] normal mode section 8.14 1 external clock test mode 6t 0 [2] unused - 5stop 0 [1] rtc source clock runs section 8.15 1 rtc clock is stopped; rtc divider chain flip-flops are asynchronously set logic 0; clkout at 32.768 khz, 16.384 khz, or 8.192 khz is still available 4tsf1 0 [1] no timestamp interrupt generated section 8.12.1 1 flag set when ts input is driven to an intermediate level between power supply and ground; flag must be cleared to clear interrupt 3por_ovrd0 [1] power-on reset override (poro) facility disabled; set logic 0 for normal operation section 8.8.2 1 poro enabled 2 12_24 0 [1] 24 hour mode selected table 22 1 12 hour mode selected 1 mi 0 [1] minute interrupt disabled section 8.13 1 minute interrupt enabled 0si 0 [1] second interrupt disabled 1 second interrupt enabled
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 10 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.2.2 register control_2 [1] default value. table 6. control_2 - control and status re gister 2 (address 01h) bit description bit symbol value description reference 7msf 0 [1] no minute or second interrupt generated section 8.13 1 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 6wdtf 0 [1] no watchdog timer interrupt or reset generated section 8.13.4 1 flag set when watchdog timer interrupt or reset generated; flag cannot be cleared by using the interface (read-only) 5tsf2 0 [1] no timestamp interrupt generated section 8.12.1 1 flag set when ts input is driven to ground; flag must be cleared to clear interrupt 4af 0 [1] no alarm interrupt generated section 8.10.6 1 flag set when alarm triggered; flag must be cleared to clear interrupt 3 cdtf 0 [1] no countdown timer interrupt generated section 8.11.4 1 flag set when countdown timer interrupt generated; flag must be cleared to clear interrupt 2tsie 0 [1] no interrupt generated from timestamp flag section 8.13.6 1 interrupt generated when timestamp flag set 1aie 0 [1] no interrupt generated from the alarm flag section 8.13.5 1 interrupt generated when alarm flag set 0 cdtie 0 [1] no interrupt generated from countdown timer flag section 8.13.2 1 interrupt generated when countdown timer flag set
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 11 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.2.3 register control_3 [1] values see table 17 . [2] default value. table 7. control_3 - control and status re gister 3 (address 02h) bit description bit symbol value description reference 7 to 5 pwrmng[2:0] [1] control of the battery switch-over, battery low detection, and extra power fail detection functions section 8.6 4btse 0 [2] no timestamp when battery switch-over occurs section 8.12.4 1 time-stamped when battery switch-over occurs 3bf 0 [2] no battery switch-ove r interrupt generated section 8.6.1 1 flag set when battery switch-over occurs; flag must be cleared to clear interrupt 2blf 0 [2] battery status ok; no battery low interrupt generated section 8.6.3 1 battery status low; flag cannot be cleared using the interface 1bie 0 [2] no interrupt generated from the battery flag (bf) section 8.13.7 1 interrupt generated when bf is set 0blie 0 [2] no interrupt generated from battery low flag (blf) section 8.13.8 1 interrupt generated when blf is set
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 12 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.3 register clkout_ctl 8.3.1 temperature compensated crystal oscillator the frequency of tuning fork quartz crystal oscillators is temperature-dependent. in the pcf2127a the frequency drift caused by tem perature variation is corrected by adjusting the load capacitance of the crystal oscillator. the load capacitance is changed by switchin g between two load capacitance values using a modulation signal with a programmable duty cy cle. every chip is ca librated in order to produce, at the measured temperature, the correct duty cycle which compensates for the frequency drift. the frequency accuracy can be evaluated by measuring the frequency of the square wave signal available at the output pin clkout. however, the selection of f clkout = 32.768 khz (default value) leads to inaccurate measurements. the most accurate frequency measurement occurs when f clkout = 1 hz is selected (see ta b l e 1 0 ). 8.3.1.1 temperature measurement the pcf2127a has a temperature sensor circuit used to perform the temperature compensation of the frequency. the temperature is measured immediately after power-on and then periodically with a period set by the temperature conversion rate tcr[1:0] in the register clkout_ctl. [1] default value. 8.3.2 clock output a programmable square wave is available at pin clkout. operation is controlled by the cof[2:0] control bits in regi ster clkout_ctl. frequencies of 32.768 khz (default) down to 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibra tion of the oscillator. clkout is an open-drain output and enabled at power-on. when disabled, the output is high-impedance. the duty cycle of the selected clock is not c ontrolled, however, due to the nature of the clock generation all but the 32 .768 khz frequencies will be 50 : 50. table 8. clkout_ctl - clko ut control register (address 0fh) bit description bit symbol value description 7 to 6 tcr[1:0] see table 9 temperature measurement period 5 to 3 - - unused 2 to 0 cof[2:0] see table 10 clkout frequency selection table 9. temperature measurement period tcr[1:0] temperature measurement period 00 [1] 4min 01 2 min 10 1 min 11 30 seconds
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 13 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal [1] duty cycle definition: % high-level time : % low-level time. [2] default value. table 10. clkout frequency selection cof[2:0] clkout frequency (hz) typical duty cycle [1] 000 [2] 32768 60 : 40 to 40 : 60 001 16384 50 : 50 010 8192 50 : 50 011 4096 50 : 50 100 2048 50 : 50 101 1024 50 : 50 110 1 50 : 50 111 clkout = high-z -
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 14 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.4 register aging_offset 8.4.1 crystal aging correction the pcf2127a has an aging offset register aging_offset to correct the crystal aging effects 2 . the accuracy of the frequency of a quartz cr ystal depends on the aging. crystal suppliers usually specify the first year aging (typically 1 ppm, maximum 3 ppm) and/or the 10 years aging (typically 5 ppm). the aging offset adds an adjustment, positive or negative, in the temperature compensation circuit which allows correcting the aging effect. the change in ppm per ao[3:0] value is different at different temperatures. at 25 c, the aging offset bits allow a frequency correction of typically 1 ppm per ao[3:0] value, from ? 7ppm to +8ppm. [1] default value. table 11. aging_offset - crystal aging offset register (address 19h) bit description bit symbol value description 7 to 4 - - unused 3 to 0 ao[3:0] see table 12 aging offset value 2. for further information please refer to the application note ref. 3 ? an10857 ? . table 12. frequency correction at 25 c, typical ao[3:0] ppm decimal binary 00000+8 10001+7 20010+6 30011+5 40100+4 50101+3 60110+2 70111+1 81000 [1] 0 91001 ? 1 10 1010 ? 2 11 1011 ? 3 12 1100 ? 4 13 1101 ? 5 14 1110 ? 6 15 1111 ? 7
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 15 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.5 general purpose 512 bytes static ram the pcf2127a contains a general purpose 512 b ytes static ram. this integrated sram is battery backed and can therefore be used to store data which is essential for the application to survive a power outage. 9 bits, ra[8:0], define the ram address pointer in registers ram_addr_msb and ram_addr_lsb. the register address pointer increments after each read or write automatically up to 1bh and then wraps around to address 00h (see figure 3 on page 6 ). data is transferred to or from the ram via the interface. to write to the ram, the register ram_wrt_cmd, to read from the ram the register ram_rd_cmd must be addressed explicitly. 8.5.1 register ram_addr_msb 8.5.2 register ram_addr_lsb 8.5.3 register ram_wrt_cmd 8.5.4 register ram_rd_cmd table 13. ram_addr_msb - ram address msb register (address 1ah) bit description bit symbol description 7 to 1 - unused 0 ra8 ram address, msb (9 th bit) table 14. ram_addr_lsb - ram address lsb re gister (address 1bh) bit description bit symbol description 7 to 0 ra[7:0] ram address, lsb (1 st to 8 th bit) table 15. ram_wrt_cmd - ram write command register (address 1ch) bit description bit symbol description 7 to 0 - data to be written into ram table 16. ram_rd_cmd - ram read command register (address 1dh) bit description bit symbol description 7 to 0 - data to be read from ram
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 16 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.5.5 operation examples 8.5.5.1 writing to the ram 1. set ram address: ? select register ram_addr_msb (send address 1ah). ? set value for bit ra8 (data byte of register 1ah). note: register address will be incremented automatically to 1bh. ? set value for array ra[7:0] (data byte of register 1bh). 2. send ram write command: ? select register ram_wrt_cmd (send address 1ch). 3. write data into the ram: ? write n data byte into ram. for details see figure 44 on page 60 . 8.5.5.2 reading from the ram 1. set ram address: ? select register ram_addr_msb (send address 1ah). ? set value for bit ra8 (data byte of register 1ah). note: register address will be incremented automatically to 1bh. ? set value for array ra[7:0] (data byte of register 1bh). 2. send ram read command: ? select register ram_rd_cmd (send address 1dh). 3. read from the ram: ? read n data byte from the ram. for details see figure 45 on page 61 .
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 17 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6 power management functions the pcf2127a has two power supply pins and one power output pin: ? v dd - the main power supply input pin ? v bat - the battery backup input pin ? bbs - battery backed output voltage pin (equal to th e internal power supply) the pcf2127a has three power management functions implemented: ? battery switch-over function ? battery low detection function ? extra power fail detection function the power management functions are controlled by the control bits pwrmng[2:0] in register control_3: [1] default value. [2] when the battery switch-over function is disabled, the pcf2127a works only with the power supply v dd ; v bat must be put to ground and the battery low detection function is disabled. table 17. power management control bit description pwrmng[2:0] function 000 [1] battery switch-over function is enabled in standard mode; battery low detection function is enabled; extra power fail detection function is enabled 001 battery switch-over function is enabled in standard mode; battery low detection function is disabled; extra power fail detection function is enabled 010 battery switch-over function is enabled in standard mode; battery low detection function is disabled; extra power fail detection function is disabled 011 battery switch-over function is enabled in direct switching mode; battery low detection function is enabled; extra power fail detection function is enabled 100 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled; extra power fail detection function is enabled 101 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled; extra power fail detection function is disabled 110 [2] battery switch-over function is disabled - only one power supply (v dd ); battery low detection function is disabled; extra power fail detection function is enabled 111 [2] battery switch-over function is disabled - only one power supply (v dd ); battery low detection function is disabled; extra power fail detection function is disabled
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 18 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6.1 battery switch-over function the pcf2127a has a backup battery switch-over circuit which monitors the main power supply v dd and automatically switches to the backup battery when a power failure condition is detected. one of two operation modes can be selected: ? standard mode: the power failure condition happens when: v dd < v bat and v dd v bat or v dd >v th(sw)bat the internal power supply is v dd . if v dd < v bat and v dd pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 19 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6.1.2 direct switching mode if v dd > v bat the internal power supply is v dd . if v dd < v bat the internal power supply is v bat . fig 4. battery switch-over behavior in standard mode with bit bie set logic 1 (enabled) 001aaj31 1 internal power supply (= v bbs ) cleared via interface backup battery operation bf v th(sw)bat (= 2.5 v) v dd (= 0 v) v bat v dd v bbs v bbs int fig 5. battery switch-over behavior in direct switching mode with bit bie set logic 1 (enabled) 001aaj31 2 internal power supply (= v bbs ) cleared via interface backup battery operation bf v th(sw)bat (= 2.5 v) v dd (= 0 v) v bat v dd v bbs v bbs int
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 20 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the direct switching mode is useful in systems where v dd is higher than v bat at all times. the direct switching mode is not recommended if the v dd and v bat values are similar (e.g. v dd = 3.3 v, v bat 3.0 v). in direct switching mo de the power consumption is reduced compared to the standard mode because the monitoring of v dd and v th(sw)bat is not performed. 8.6.1.3 battery switch-over disabled: only one power supply (v dd ) when the battery switch-over function is disabled: ? the power supply is applied on the v dd pin ? the v bat pin must be connected to ground ? the internal power supply, available at the output pin bbs, is equal to v dd ? the battery flag (bf) is always logic 0 8.6.1.4 battery switch-over architecture the architecture of the battery switch-over circuit is shown in figure 6 . the internal power supply (ava ilable on pin bbs) is equal to v dd or v bat . it has to be assured that there are decoupling capacitors on the pins v dd , v bat , and bbs. 8.6.2 battery backup supply the v bbs voltage on the output pi n bbs is equal to the intern al power supply, depending on the selected battery switch-over function mode: the output pin bbs can be used as a supply for external device s with battery backup needs, such as sram (see ref. 3 ? an10857 ? ). for this case, figure 7 shows the typical driving capability when v bbs is driven from v dd . fig 6. battery switch-over circuit, simplified block diagram 001aag06 1 v cc v th(sw)bat v dd v bbs (internal power supply) v dd v dd(int) v dd(int) v dd(int) v bat logic comparators logic switches v cc v th(sw)bat v bat table 18. output pin bbs battery switch-ove r function mode conditions v bbs equals standard v dd > v bat or v dd > v th(sw)bat v dd v dd < v bat and v dd < v th(sw)bat v bat direct switching v dd > v bat v dd v dd < v bat v bat disabled only v dd available, v bat must be put to ground v dd
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 21 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6.3 battery low detection function the pcf2127a has a battery low detection circui t which monitors the st atus of the battery v bat . when v bat drops below the threshold value v th(bat)low (typically 2.5 v) the blf flag (register control_3) is set to indicate that th e battery is low and that it must be replaced. monitoring of the battery voltage also occurs during battery operation. an unreliable battery cannot prevent that the supply voltage drops below v low (typical 1.2 v) and therewith the data integrity gets lost. when v bat drops below the threshold value v th(bat)low , the following sequence occurs (see figure 8 ): 1. the battery low flag blf is set logic 1. 2. an interrupt is generated if the control bit blie (register control_3) is enabled (see section 8.13.8 ). 3. the flag blf remains logic 1 until the battery is replaced. blf cannot be cleared using the interface. it is cleared automatica lly by the battery low detection circuit when the battery is replaced. fig 7. typical driving capability of v bbs : (v bbs ? v dd ) with respect to the output load current i bbs i bbs (ma) 0 8 6 4 2 001aaj327 ? 400 ? 600 ? 200 0 v bbs ? v dd (mv) ? 800 v dd = 4.2 v v dd = 3 v v dd = 2 v
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 22 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6.4 extra power fail detection function the pcf2127a has an extra power fail detection circuit which compares the voltage at the power fail input pin pfi to an internal reference voltage equal to 1.25 v. if v pfi < 1.25 v the power fail output pfo is driven low. pfo is an open-drain, active low output which requires an external pull-up resistor in any application. the extra power fail detection function is typica lly used as a low voltage detection for the main power supply v dd (see figure 9 ). usually r1 and r2 should be chosen such that the voltage at pin pfi ? is higher than 1.25 v at start-up ? falls below 1.25 v when v dd falls below a desired threshold voltage, v th(uvp) , defined by equation 1 : fig 8. battery low detection behavior with bit blie set logic 1 (enabled) 001aaj32 2 internal power supply (= v bbs ) v bat blf v th(bat)low (= 2.5 v) v bat v dd = v bbs int fig 9. typical application of the extra power fail detection function 001aaj67 8 pfo pfi 15 14 r pu v dd v ss r1 r2 pcf2127a 1.25 v (internal)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 23 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal (1) v th(uvp) value is usually set to a value that there are several milliseconds before v dd falls below the minimum operating voltage of the sys tem, in order to allow the microcontroller to perform early backup operations. if the extra power fail detection function is not used, pin pfi must be connected to v ss and pin pfo must be left open circuit. 8.6.4.1 extra power fail detection when the battery switch over function is enabled ? when the power switches to the backup battery supply v bat , the power fail comparator is switched off and the power fail output at pin pfo goes (or remains) low ? when the power switches back to the main v dd , the pin pfo is not driven low anymore and is pulled high through the exte rnal pull-up resistance for a certain time (t rec = 15.63 ms to 31.25 ms) and then the power fail comparator is enabled again for illustration see figure 10 and figure 11 . v th uvp () r 1 r 2 ----- - 1 + ?? ?? 1.25v = fig 10. pfo signal behavior when battery switch-over is enabled in standard mode and v th(uvp) >(v bat ,v th(sw)bat ) 001aaj31 9 internal power supply (= v bbs ) comparator enabled comparator disabled comparator enabled v th(sw)bat (= 2.5 v) v bat v dd v bbs v bbs v th(uvp) pf0 t rec = [15.63 : 31.25] ms v dd (= 0 v)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 24 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.6.4.2 extra power fail detection when the battery switch-over function is disabled if the battery switch-over function is disabled and the power fail comparator is enabled, the power fail output at pin pfo depends only on the result of the comparison between v pfi and 1.25 v: ? if v pfi > 1.25 v, pfo = high (through the external pull-up resistor) ? if v pfi < 1.25 v, pfo = low fig 11. pfo signal behavior when battery switch-over is enabled in direct switching mode and v th(uvp) < v bat 001aaj32 0 internal power supply (= v bbs ) comparator enabled comparator disabled comparator enabled v th(sw)bat (= 2.5 v) v th(uvp) v dd v bbs v bbs v bat pf0 t rec v dd (= 0 v) fig 12. pfo signal behavior when battery switch-over is disabled 001aaj32 1 comparator always enabled v th(sw)bat (= 2.5 v) v dd v th(uvp) pf0
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 25 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.7 oscillator stop detection function the pcf2127a has an on-chip os cillator detection circuit which monitors the status of the oscillation: whenever the oscilla tion stops, a reset occurs a nd the oscillator stop flag osf (in register seconds) is set logic 1. ? power-on: a. the oscillator is not running, the chip is in reset (pin rst is low and flag osf is logic 1). b. when the oscillator starts running and is st able after power-on, the chip exits from reset (pin rst is high). c. the flag osf is still logic 1 and can be cleared (osf set logic 0) via the interface. ? power supply failure: a. when the power supply of the chip (v dd or v bat ) drops below a certain value (v low ), typically 1.2 v, the oscillator stops running and a reset occurs. b. when the power supply retu rns to normal operation, th e oscillator starts running again, the chip exits from reset. c. the flag osf is still logic 1 and can be cleared (osf set logic 0) via the interface. (1) theoretical state of the signals since there is no power. (2) the oscillator stop flag (osf), se t logic 1, indicates that the osci llation has stopped and a reset has occurred since the flag was last cleared (osf set l ogic 0). in this case the integrity of the clock information is not guaranteed. the osf flag is cleared using the interface. fig 13. power failure event due to battery discharge: reset occurs 001aaj40 9 internal power supply (1) v th(sw)bat (= 2.5 v) v ss v bat v low (= 1.2 v) v dd v bbs v bbs v bbs v bbs v dd v bat v ss (2) osf battery discharge
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 26 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.8 reset function the pcf2127a has an active low open-drain output reset pin (rst ). the reset output is activated at power-on reset (por) and whenever th e oscillator is stopped (see section 8.7 ). 8.8.1 power-on reset (por) the por is active whenever t he oscillator is stopped. the osc illator is also considered to be stopped during the time between power -on and stable crystal resonance (see figure 14 ). this time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. whenever an internal reset occurs, the osc illator stop flag is set (osf set logic 1). after por, the following mode is entered: ? 32.768 khz clkout active ? power-on reset override (poro) available to be set ? 24 hour mode is selected ? battery switch-over is enabled ? battery low detection is enabled ? extra power fail detection is enabled the register values after power-on are shown in table 4 . 8.8.2 power-on reset override (poro) the por duration is directly rela ted to the crystal o scillator start-up time. due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the por and therefore speed up on-board test of the device. fig 14. dependency between por and oscillator 013aaa24 3 chip in reset chip not in reset t v dd oscillation rst
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 27 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the setting of the poro mode requires that por_ovrd in register control_1 is set logic 1 and that the signals at the interface pins sda/ce and scl are toggle d as illustrated in figure 16 . all timings shown are required minimum. once the override mode is entered, the devi ce is immediately released from the reset state and the set-up operation can commence. the poro mode is cleared by writing lo gic 0 to por_ovrd. por_ovrd must be logic 1 before a re-entry into the overri de mode is possible. setting por_ovrd logic 0 during normal operation has no effect except to prevent accidental entry into the poro mode. fig 15. power-on reset (por) system fig 16. power-on reset override (poro) sequence, valid for both i 2 c-bus and spi-bus 001aaj32 4 oscillator 0 = override inactive 1 = override active 0 = clear override mode 1 = override possible por_ovrd sda/ce scl reset override clear osc stopped 0 = stopped, 1 = running reset 001aaj32 6 minimum 2000 ns minimum 500 ns 8 ms power up scl reset override sda/ce
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 28 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.9 time and date function the majority of these registers are coded in the binary coded decimal (bcd) format. 8.9.1 register seconds [1] start-up value. 8.9.2 register minutes table 19. seconds - seconds and clock integrit y register (address 03h) bit description bit symbol value place value description 7 osf 0 - clock integrity is guaranteed 1 [1] - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to 4 seconds 0 to 5 ten?s place actual seconds coded in bcd format 3to0 0to9 unit place table 20. seconds coded in bcd format seconds value in decimal upper-digit (ten?s place) digit (unit place) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001 table 21. minutes - minutes register (address 04h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 ten?s place actual minutes coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 29 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.9.3 register hours [1] hour mode is set by the bit 12_24 in register control_1. 8.9.4 register days [1] the rtc compensates for leap years by adding a 29 th day to february if the year counter contains a value which is exactly divisible by 4, in cluding the year 00. 8.9.5 register weekdays although the association of the weekdays coun ter to the actual weekday is arbitrary, the pcf2127a will assume sunday is 000 and monday is 001 for the pur poses of determining the increment for calendar weeks. [1] these bits may be re-assigned by the user. table 22. hours - hours register (address 05h) bit description bit symbol value place value description 7to6 - - - unused 12 hour mode [1] 5 ampm 0 - indicates am 1 - indicates pm 4 hours 0 to 1 ten?s place actual hours coded in bcd format when in 12 hour mode 3to0 0to9 unit place 24 hour mode [1] 5 to 4 hours 0 to 2 ten?s place actual hours coded in bcd format when in 24 hour mode 3to0 0to9 unit place table 23. days - days register (a ddress 06h) bit description bit symbol value place value description 7to6 - - - unused 5to4 days [1] 0 to 3 ten?s place actual day coded in bcd format 3to0 0to9 unit place table 24. weekdays - weekdays register (address 07h) bit description bit symbol value description 7to3 - - unused 2 to 0 weekdays 0 to 6 actual weekday value, see ta b l e 2 5 table 25. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday110
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 30 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.9.6 register months 8.9.7 register years 8.9.8 setting and reading the time figure 17 shows the data flow and data dependencies starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. this prevents ? faulty reading of the clock and calendar during a carry condition ? incrementing the time regist ers during the read cycle table 26. months - months register (address 08h) bit description bit symbol value place value description 7to5 - - - unused 4 months 0 to 1 ten?s place actual month coded in bcd format, see table 27 3to0 0to9 unit place table 27. month assignments in bcd format month upper-digit (ten?s place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april00100 may00101 june00110 july00111 august01000 september 0 1 0 0 1 october10000 november10001 december10010 table 28. years - years register (address 09h) bit description bit symbol value place value description 7 to 4 years 0 to 9 ten?s place actual year coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 31 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal after this read/write access is completed, the time circuit is released again and any pending request to increment the time counte rs that occurred during the read/write access is serviced. a maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see figure 18 ). as a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method co uld result in the time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. a similar problem exists when reading. a roll over may occur between reads thus giving the minutes from one moment and the hours from the next. therefore it is advised to read all time and date registers in one access. fig 17. data flow of the time function fig 18. access time for read/write operations 001aaf90 1 1 hz tick 12_24 hour mode weekday seconds minutes hours days leap year calculation months years t < 1 s 013aaa21 5 slave address data stop data start
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 32 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.10 alarm function when one or more of the alarm bit fields are loaded with a valid second, minute, hour, day, or weekday and its corresponding alarm enable bit (ae_x) is logic 0, then that information is compared with the actual second, minute, hour, day, and weekday (see figure 19 ). the generation of interrupts from the alarm function is described in section 8.13.5 . 8.10.1 register second_alarm [1] default value. (1) only when all enabled alarm settings are matching. fig 19. alarm function block diagram 013aaa236 weekday alarm ae_w weekday time = day alarm ae_d day time = hour alarm ae_h hour time = minute alarm = check now signal set alarm flag af (1) ae_s = 1 1 0 example ae_m minute time = second time second alarm ae_s table 29. second_alarm - second alarm register (address 0ah) bit description bit symbol value place value description 7 ae_s 0 - second alarm is enabled 1 [1] - second alarm is disabled 6 to 4 second_alarm 0 to 5 ten?s place second alarm information coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 33 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.10.2 register minute_alarm [1] default value. 8.10.3 register hour_alarm [1] default value. [2] hour mode is set by the bit 12_24 in register control_1. 8.10.4 register day_alarm [1] default value. table 30. minute_alarm - minute alarm register (address 0bh) bit description bit symbol value place value description 7 ae_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 ten?s place minute alarm information coded in bcd format 3to0 0to9 unit place table 31. hour_alarm - hour alarm regist er (address 0ch) bit description bit symbol value place value description 7 ae_h 0 - hour alarm is enabled 1 [1] - hour alarm is disabled 6 - - - unused 12 hour mode [2] 5 ampm 0 - indicates am 1 - indicates pm 4 hour_alarm 0 to 1 ten?s place hour alarm information coded in bcd format when in 12 hour mode 3to0 0to9 unit place 24 hour mode [2] 5 to 4 hour_alarm 0 to 2 ten?s place hour alarm information coded in bcd format when in 24 hour mode 3to0 0to9 unit place table 32. day_alarm - day rearm regist er (address 0dh) bit description bit symbol value place value description 7 ae_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 ten?s place day alarm information coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 34 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.10.5 register weekday_alarm [1] default value. 8.10.6 alarm flag when all enabled comparisons first match, the alarm flag af (register control_2) is set. af will remain set until cleared by using the interf ace. once af has been cleared it will only be set again when the time increments to match the alarm condition once more. for clearing the flags see section 8.11.6 alarm registers which have their alarm enable bit ae_x at logic 1 are ignored. table 33. weekday_alarm - weekday alarm regi ster (address 0eh) bit description bit symbol value description 7 ae_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6to3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information example where only the minute alarm is used and no other interrupts are enabled. fig 20. alarm flag timing diagram 001aaf9 03 44 45 45 minute alarm minutes counter af int when aie = 1 46
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 35 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.11 timer functions the pcf2127a has two different timer func tions, a watchdog timer and a countdown timer. the timers can be selected by using th e control bits wd_cd[1:0] in the register watchdg_tim_ctl. ? the watchdog timer has four selectable source clocks. it can, for example, be used to detect a microprocessor with in terrupt and reset capability wh ich is out of control (see section 8.11.3 ) ? the countdown timer has four selectable source clocks allowing for countdown periods from less than 1 ms to more than 4 hours (see section 8.11.4 ) to control the timer functions and timer output , the registers control_2, watchdg_tim_ctl, and watchdg_tim_val are used. 8.11.1 register watchdg_tim_ctl [1] default value. table 34. watchdg_tim_ctl - watchdog timer cont rol register (address 10h) bit description bit symbol value description 7 to 6 wd_cd[1:0] 00 [1] watchdog timer disabled; countdown timer disabled 01 watchdog timer disabled; countdown timer enabled if cdtie is set logic 1, the interrupt pin int is activated when the countdown timed out 10 watchdog timer enabled; the interrupt pin int is activated when timed out; countdown timer not available 11 watchdog timer enabled; the reset pin rst is activated when timed out; countdown timer not available 5ti_tp 0 [1] the interrupt pin int is configured to generate a permanent active signal when msf and/or cdtf is set 1 the interrupt pin int is configured to generate a pulsed signal when msf flag and/or cdtf flag is set (see figure 25 ) 4to2 - - unused 1 to 0 tf[1:0] timer source clock for watchdog and countdown timer 00 4.096 khz 01 64 hz 10 1 hz 11 [1] 1 ? 60 hz
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 36 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.11.2 register watchdg_tim_val 8.11.3 watchdog timer function the watchdog timer function is controlled by the wd_cd[1:0] bits of the register watchdg_tim_ctl (see ta b l e 3 4 ). the two bits tf[1:0] in register watchdg_tim_ ctl determine one of the four source clock frequencies for the watchdog timer: 4.096 khz, 64 hz, 1 hz, or 1 ? 60 hz (see ta b l e 3 6 ). when the watchdog timer functi on is enabled, the 8 bit timer in register watchdg_tim_val (see table 35 ) determines the wa tchdog timer period. the watchdog timer counts down from the software programmed 8 bit binary value n in register watchdg_tim_val. when the counte r reaches 1 the watchdog timer flag wdtf (register control_2) is set logic 1. in the case that wdtf is logic 1: ? if wd_cd[1:0] = 10 an interrupt will be generated ? if wd_cd[1:0] = 11 a reset will be generated the counter does not automatically reload. when wd_cd[1:0] = 10 or wd_cd[1:0] = 11 an d the microcontroller unit (mcu) loads a watchdog timer value n: ? the flag wdtf is reset ? int or rst is cleared ? the watchdog timer starts again loading the counter with 0 will: ? reset the flag wdtf ? clear int or rst ? stop the watchdog timer table 35. watchdg_tim_val - watchdog timer value register (address 11h) bit description bit symbol value description 7 to 0 watchdg_tim_val[7:0] 00 to ff countdown period in seconds: where n is the countdown value table 36. programmable watchdog or countdown timer tf[1:0] timer source clock frequency units minimum timer period (n = 1) units maximum timer period (n = 255) units 00 4.096 khz 244 s 62.256 ms 01 64 hz 15.625 ms 3.984 s 10 1 hz 1 s 255 s 11 1 ? 60 hz 60 s 15300 s countdownperiod n sourceclockfrequency -------------------------------------------------------------- - =
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 37 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal remark: wdtf is read only and cannot be clear ed with the interface. wdtf can be cleared by: ? loading a value in register watchdg_tim_val ? reading of the register control_2 writing a logic 0 or logic 1 to wdtf has no effect. ? when the watchdog timer counter reaches 1, the watchdog timer flag wdtf is set logic 1 ? when a minute or second interrupt occurs, the minute/second flag msf is set logic 1 (see section 8.13.1 ) counter reached 1, wdtf is set logic 1, and an interrupt is generated. fig 21. wd_cd[1:0] = 10: watchdog activates an interrupt when timed out counter reached 1, wdtf is set logic 1, reset pulse on the rst pin is generated for a time equal to t w(rst) . fig 22. wd_cd[1:0] = 11: watchdog acti vates a reset pulse when timed out 001aag06 2 watchdog timer value wdtf n = 1 n mcu int 001aag06 3 watchdog timer value wdtf t w(rst) n = 1 n mcu rst
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 38 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.11.4 countdown timer function the countdown timer function is controlled by the wd_cd[ 1:0] bits in register watchdg_tim_ctl (see ta b l e 3 4 ). the timer counts down from the software programmed 8 bit binary value n in register watchdg_tim_val. when the counter reaches 1 ? the countdown timer flag cdtf is set ? the counter automa tically reloads ? and the next time period starts loading the counter with 0 effectively stops the timer. reading the timer will return the actu al value of the countdown counter. if a new value of n is written before the end of the actual timer peri od, this value will take immediate effect. it is not recommended to change n without first disabling the counter by setting wd_cd[1:0] = 00. the update of n is asynchronous to the timer clock. therefore changing it on the fly could result in a corrupted value loaded into the countdown counter. this can result in an undetermined countdown period for the first period. the countdown value n will, however, be corr ectly stored and correctly loaded on su bsequent timer periods. table 37. specification of t w(rst) wd_cd[1:0] tf[1:0] t w(rst) 11 00 244 s 01 15.625 ms 10 15.625 ms 11 15.625 ms in this example it is assumed that the count down timer flag (cdtf) is cleared before the next countdown period expires and that int is set to pulsed mode. fig 23. general countdown timer behavior 001aag071 countdown value, n timer source clock countdown counter wd/cd [1:0] cdtf int 02 03 00 01 xx 03 xx 01 03 02 01 03 02 n duration of first timer period after enable may range from n ? 1 to n+1 n 01 03
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 39 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal when the countdown timer flag cdtf is set, an interrup t signal on int will be generated provided that this mode is enabled. see section 8.13.2 for details on how the interrupt can be controlled. when starting the countdown ti mer for the first time, only th e first period will not have a fixed duration. the amount of inaccuracy fo r the first timer period will depend on the chosen source clock, see ta b l e 3 8 . at the end of every countdown, the timer sets the countdown timer flag (cdtf). cdtf may only be cleared by software. the asserted cdtf can be used to generate an interrupt (int ). the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of cdtf. ti_tp is used to control this mode sele ction. the interrupt output ma y be disabled with the cdtie bit, see ta b l e 6 . when reading the timer, the actual countdown value is returned and not the initial value n. since it is not possible to freeze the count down timer counter during read back, it is recommended to read the register twice and check for consistent results. 8.11.5 pre-defined timers: second and minute interrupt pcf2127a has two pre-defined timers which are used to generate an interrupt either once per second or once per minute. the pulse generator for the minute or second interrupt operates from an internal 64 hz clock. it is independent of the watchdog or countdown timers. each of these timers can be enabled by the bits si (second interrupt) and mi (minute interrupt) in register control_1. 8.11.6 clearing flags the flags msf, cdtf, af and tsfx can be clea red by using the interface. to prevent one flag being overwritten while clearing another, a logic and is performed during the write access. a flag is cleared by writing logic 0 wh ilst a flag is not cleared by writing logic1. writing logic1 will result in the flag value remaining unchanged. four examples are given for clearing the fl ags. clearing the flags is made by a write command: ? bits labeled with - must be wri tten with their previous values ? wdtf is read only and has to be written with logic 0 repeatedly re-writing these bits has no influence on the functional behavior. table 38. first period de lay for timer counter timer source clock minimum timer period maximum timer period 4.096 khz n n + 1 64 hz n n + 1 1 hz (n ? 1) + 1 ? 64 hz n + 1 ? 64 hz 1 ? 60 hz (n ? 1) + 1 ? 64 hz n + 1 ? 64 hz table 39. flag location in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 msf wdtf tsf2 af cdtf - - -
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 40 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the following tables show what instruction mu st be sent to clear the appropriate flag. [1] the bits labeled as - have to be re written with the previous values. [1] the bits labeled as - have to be re written with the previous values. [1] the bits labeled as - have to be re written with the previous values. [1] the bits labeled as - have to be re written with the previous values. table 40. example values in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 10111000 table 41. example to clear only cdtf (bit 3) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 1 0 1 1 0 - [1] - [1] - [1] table 42. example to clear only af (bit 4) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 1 0 1 0 1 0 [1] 0 [1] 0 [1] table 43. example to clear only msf (bit 7) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 0 0 1 1 1 0 [1] 0 [1] 0 [1] table 44. example to clear both cdtf and msf in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 0 0 1 1 0 0 [1] 0 [1] 0 [1]
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 41 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.12 timestamp function the pcf2127a has an active low timestamp input pin ts , internally pulled with an on-chip pull-up resistor to the internal power supply of the device. it also has a timestamp detection circuit which can detect two different events: 1. input on pin ts is driven to an inte rmediate level between power supply and ground. 2. input on pin ts is driven to ground. the timestamp function is enabled by default af ter power-on and it can be switched off by setting the control bit tsof f (register timestp_ctl). a most common application of the timestamp function is described in ref. 3 ? an10857 ? . see section 8.13.6 for a description of interrupt gene ration from the timestamp function. 8.12.1 timestamp flag 1. when the ts input pin is driven to an intermediate level between the power supply and ground the following sequence occurs: a. the actual date and time are stored in the timestamp registers. b. the timestamp flag tsf1 (register control_1) is set. c. if the tsie bit (register control_2) is active, an interrupt on the int pin is generated. the tsf1 flag can be cleared by using the interface. clearing the flag will clear the interrupt. once tsf1 is cleared it will only be set again when a new negative edge on ts is detected. 2. when the ts input pin is driven to ground the following sequence occurs: a. the actual date and time are stored in the timestamp registers. b. in addition to the tsf1 flag the ts f2 flag (register control_2) is set. c. if the tsie bit is active, an interrupt on the int pin is generated. fig 24. timestamp detection with two push-buttons on one the ts pin (e.g. for tamper detection) 116 pcf212xa 215 314 413 512 611 710 89 ts v ss v dd 013aaa17 6 r2 = 200 k 5 % r1 = 200 k 20 % push-button 1 connected to cover 1 push-button 2 connected to cover 2
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 42 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the tsf1 and tsf2 flags can be cleared by using the interface; clearing both flags will clear the interrupt. once tsf2 is cleared it will only be set again when ts pin is driven to ground once again. 8.12.2 time stamp mode the timestamp function has two different modes selected by the control bit tsm (timestamp mode) in register timestp_ctl: ? if tsm is logic 0 (default): in subsequent tr igger events without clearing the timestamp flags, the last timestamp event is stored ? if tsm is logic 1: in subsequent trigger events without clearing the timestamp flags, the first timestamp event is stored the timestamp function also depends on the control bit btse in register control_3, see section 8.12.4 . 8.12.3 timestamp registers 8.12.3.1 register timestp_ctl [1] default value. 8.12.3.2 register sec_timestp 8.12.3.3 register min_timestp table 45. timestp_ctl - timestamp control register (address 12h) bit description bit symbol value description 7tsm 0 [1] in subsequent events without clearing the timestamp flags, the last event is stored 1 in subsequent events without clearing the timestamp flags, the first event is stored 6tsoff 0 [1] timestamp function active 1 timestamp function disabled 5 - - unused 4 to 0 1_o_16_timestp[4:0] 1 ? 16 second timestamp information coded in bcd format table 46. sec_timestp - second timestamp re gister (address 13h) bit description bit symbol value place value description 7 - - - unused 6 to 4 second_timestp 0 to 5 ten?s place second timestamp information coded in bcd format 3to0 0to9 unit place table 47. min_timestp - minute timestamp register (address 14h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minute_timestp 0 to 5 ten?s place minute timestamp information coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 43 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.12.3.4 register hour_timestp [1] hour mode is set by the bit 12_24 in register control_1. 8.12.3.5 register day_timestp 8.12.3.6 register mon_timestp 8.12.3.7 register year_timestp table 48. hour_timestp - hour timestamp register (address 15h) bit description bit symbol value place value description 7to6 - - - unused 12 hour mode [1] 5 ampm 0 - indicates am 1 - indicates pm 4 hour_timestp 0 to 1 ten?s place hour timestamp information coded in bcd format when in 12 hour mode 3to0 0to9 unit place 24 hour mode [1] 5 to 4 hour_timestp 0 to 2 ten?s place hour timestamp information coded in bcd format when in 24 hour mode 3to0 0to9 unit place table 49. day_timestp - day timestamp regi ster (address 16h) bit description bit symbol value place value description 7to6 - - - unused 5 to 4 day_timestp 0 to 3 ten?s place day timestamp information coded in bcd format 3to0 0to9 unit place table 50. mon_timestp - month timestamp register (address 17h) bit description bit symbol value place value description 7to5 - - - unused 4 month_timestp 0 to 1 ten?s place month timestamp information coded in bcd format 3to0 0to9 unit place table 51. year_timestp - year timestamp re gister (address 18h) bit description bit symbol value place value description 7 to 4 year_timestp 0 to 9 ten?s place year timestamp information coded in bcd format 3to0 0to9 unit place
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 44 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.12.4 dependency between battery switch-over and timestamp the timestamp function depends on the co ntrol bit btse in register control_3: [1] default value. table 52. battery switch-over and timestamp btse bf description 0- [1] the battery switch-over does not affect the timestamp registers 1 if a battery switch-over event occurs: 0 [1] the timestamp registers store the time and date when the switch-over occurs; after this event occurr ed bf is set logic 1 1 the timestamp registers are not modified; in this condition subsequent battery switch-over events or falling edges on pin ts are not registered
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 45 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.13 interrupt output, int pcf2127a has an interrupt output pin int which is open-drain, active low. interrupts may be sourced from different places: ? second or minute timer ? countdown timer when si, mi, cdtie, wd_cd, aie, tsie, bie, blie are all disabled, int will remain high-impedance. fig 25. interrupt block diagram blf: battery low flag set set battery low flag, blf to interface: read blf blie 001aag070 from battery low detection circuit: clear bf clear bf: battery flag set set battery flag, bf to interface: read bf bie from interface: clear bf clear tsfx: timestamp flag set set timestamp flag, tsfx to interface: read tsfx tsie from interface: clear tsfx clear af: alarm flag set set alarm flag, af to interface: read af aie from interface: clear af clear wdtf: watchdog timer flag set watchdog counter to interface: read wdtf wd_cd[1:0] = 00 wd_cd[1:0] = 01 mcu loading watchdog counter clear cdtf: countdown timer flag set countdown counter to interface: read cdtf cdtie int pin 0 1 wd_cd[1:0] = 01 from interface: clear cdtf clear pulse generator 2 trigger clear msf: minute second flag set minutes counter seconds counter to interface: read msf si/mi ti_tp 0 1 from interface: clear msf clear si mi pulse generator 1 trigger clear
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 46 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal ? watchdog timer ? alarm ? timestamp ? battery switch-over ? battery low detection the control bit ti_tp (register watchdg_tim_ ctl) is used to configure whether the interrupts generated from the second/minute timer (flag msf in register control_2) and the countdown timer (flag cdtf in register control_2) are pulsed signals or a permanently active signal. all the other inte rrupt sources generate a permanently active interrupt signal which follows the status of the corresponding flags. when the interrupt sources are all disabled, int remains high-impedance. ? the flags msf, cdtf, af, tsfx and bf can be cleared by using the interface ? the flags wdtf is read only. how it can be cleared is explained in section 8.11.6 ? the flag blf is read only. it is cleared automatically from the battery low detection circuit when the battery is replaced 8.13.1 minute and second interrupts minute and second interrupts are generate d by predefined timers. the timers can be enabled independently from one another by the bits mi and si in register control_1. however, a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time. the minute/second flag msf (register control_2) is set logic 1 when either the seconds or the minutes counter increments according to the actually enabled interrupt (see ta b l e 5 3 ). the msf flag can be read and cleared by the interface. when msf is set logic 1: ? if ti_tp is logic 1 the interrupt is generated as a pulsed signal. ? if ti_tp is logic 0 the interrupt is permanent ly active signal that remains until msf is cleared. table 53. effect of bits mi and si on pin int and bit msf mi si result on int result on msf 0 0 no interrupt generated msf never set 1 0 an interrupt once per minute msf set when minutes counter increments 0 1 an interrupt once per second msf set when seconds counter increments 1 1 an interrupt once per second msf set when seconds counter increments
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 47 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the pulse generator for the minute/second interrupt operates from an internal 64 hz clock and generates a pulse of 1 ? 64 seconds in duration. 8.13.2 countdown timer interrupts the generation of interrupts from the countdown timer is controlled via the cdtie bit (register control_2). the interrupt may be generated as a pulsed si gnal at every countdown period or as a permanently active signal which follows the st atus of the countdown timer flag cdtf. bit ti_tp is used to control this bit. in this example, bit ti_tp is logic 1 and the msf flag is not cleared after an interrupt. fig 26. int example for si and mi when ti_tp is logic 1 in this example, bit ti_tp is logic 0 an d the msf flag is cleared after an interrupt. fig 27. int example for si and mi when ti_tp is logic 0 001aaf9 05 58 59 59 00 11 seconds counter minutes counter int when si enabled msf when si enabled int when only mi enabled msf when only mi enabled 12 00 01 001aag0 72 58 seconds counter minutes counter int when si enable msf when si enable int when only mi enabled msf when only mi enabled 59 59 11 00 00 01 12
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 48 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.13.3 int pulse shortening the pulse generator for the countdown timer interr upt also uses an internal clock, but this time it is dependent on the selected sour ce clock for the countdown timer and on the countdown value n. as a consequence, the width of the interrupt pulse varies (see ta b l e 5 4 ). [1] n = loaded countdown value. timer stopped when n = 0. if the msf or cdtf flag (register control _2) is cleared before the end of the int pulse, then the int pulse is shortened. this allows the source of a system interrupt to be cleared immediately when it is serviced , i.e. the system does not have to wait for the completion of the pulse before continuing; see figure 28 and figure 29 . instructions for clearing bit msf and bit cdtf can be found in section 8.11.6 . table 54. int operation (bit ti_tp = 1) source clock (hz) int period (s) n = 1 [1] n > 1 4096 1 ? 8192 1 ? 4096 64 1 ? 128 1 ? 64 1 1 ? 64 1 ? 64 1 ? 60 1 ? 64 1 ? 64 (1) indicates normal duration of int pulse. the timing shown for clearing bit msf is also va lid for the non-pulsed interrupt mode, i.e. when ti_tp is logic 0, where the int pulse may be shortened by setting both bits mi and si logic 0. fig 28. example of shortening the int pulse by clearing the msf flag 001aaf9 08 58 seconds counter msf int scl instruction 59 clear instruction 8th clock (1)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 49 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.13.4 watchdog timer interrupts the generation of interrupts from the watchdog timer is controlled using the wd_cd[1:0] bits (register watchdg_tim_ctl). the interrupt is generated as an active signal which follows the status of the watchdog timer flag wdtf (register control_2). no pulse generation is possible fo r watchdog timer interrupts. the interrupt is cleared when the flag wdtf is reset. wdtf is a read only bit and cannot be cleared by using the interface. instructions for clearing it can be found in section 8.11.6 . 8.13.5 alarm interrupts generation of interrupts from the alarm function is controlled via the bit aie (register control_2). if aie is enabled, the int pin will follow the status of bit af (register control_2). clearing af will immediately clear int . no pulse generation is possible for alarm interrupts. (1) indicates normal duration of int pulse. the timing shown for clearing cdtf is also vali d for the non-pulsed interrupt mode, i.e. when ti_tp is logic 0, where the int pulse may be shortened by setting cdtie logic 0. fig 29. example of shortening the int pulse by clearing the cdtf flag 001aaf9 09 01 countdown counter cdtf int scl instruction n clear instruction 8th clock (1) example where only the minute alarm is used and no other interrupts are enabled. fig 30. af timing diagram 001aaf9 10 44 45 minute counter minute alarm af int scl instruction 45 clear instruction 8th clock
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 50 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.13.6 timestamp interrupts interrupt generation from the timestamp function is controlled using the tsie bit (register control_2). if tsie is enabled the int pin follows the status of the flags tsfx. clearing the flags tsfx immediately clears int . no pulse generation is possible for timestamp interrupts. 8.13.7 battery switch-over interrupts generation of interrupts from the battery swit ch-over is controlled via the bie bit (register control_3). if bie is enabled, the int pin follows the status of bit bf in register control_3 (see table 52 ). clearing bf immediately clears int . no pulse generation is possible for battery switch-over interrupts. 8.13.8 battery low detection interrupts generation of interrupts from the battery low detection is controlled via the blie bit (register control_3). if bl ie is enabled the int pin will follow the status of bit blf (register control_3). the interrupt is cl eared when the battery is replaced (blf is logic 0) or when bit blie is disabled (blie is logic 0). blf is read only and therefore cannot be cleared via the interface.
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 51 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.14 external clock test mode a test mode is available which allows on-board test ing. in this mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit ext_test logic 1 (register control_1). then pin clkout becomes an input. the test mode repl aces the internal clock signal (64 hz) with the signal applied to pin clkout. ever y 64 positive edges applied to pin clkout generate an increment of one second. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the internal cl ock, now sourced from clkout, is divided down by a 2 6 divider chain called prescaler (see prescaler in table 55 ). the prescaler can be set into a known state by using bit stop. when bit stop is logic 1, the prescaler is reset to 0. stop must be cleared before the prescaler can operate again. from a stop condition, the fi rst 1 second increment will take place after 32 positive edges on pin clkout. thereafter, every 64 posit ive edges will cause a 1 second increment. remark: entry into test mode is not synchroni zed to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. operating example: 1. set ext_test test mode (registe r control_1, ext_test is logic 1). 2. set bit stop (register co ntrol_1, stop is logic 1). 3. set time registers to desired value. 4. clear stop (register control_1, stop is logic 0). 5. apply 32 clock pulses to clkout. 6. read time registers to see the first change. 7. apply 64 clock pulses to clkout. 8. read time registers to see the second change. repeat 7 and 8 for additional increments.
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 52 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 8.15 stop bit function the function of the stop bit is to allow for ac curate starting of the time circuits. stop will cause the upper part of the prescaler (f 9 to f 14 ) to be held in reset and thus no 1 hz ticks are generated. the time circuits can then be set an d will not increment until the stop bit is released. stop will not affect the clkout si gnal but the output of the prescaler in the range of 32 hz to 1 hz (see figure 31 ). the lower stages of the prescaler, f 0 to f 8 , are not reset and because the i 2 c-bus and the spi-bus are asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits is between 0 and one 64 hz cycle (0.484375 s and 0.500000 s), see table 55 and figure 32 . [1] f 0 is clocked at 32.768 khz. table 55. first increment of time circuits after stop release bit stop prescaler bits [1] f 0 to f 8 - f 9 to f 14 1hz tick time hh:mm:ss comment clock is running normally 0 010000111-010100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 to f 8 are not reset and values cannot be predicted externally 1 xxxxxxxxx-000000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xxxxxxxxx-000000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xxxxxxxxx-000000 08:00:00 prescaler is now running 0 xxxxxxxxx-100000 08:00:00 0 xxxxxxxxx-100000 08:00:00 0 xxxxxxxxx-110000 08:00:00 :: : 0 111111111-111110 08:00:00 0 000000000-000001 08:00:01 0 to 1 transition of f 14 increments the time circuits 0 100000000-000001 08:00:01 :: : 0 111111111-111111 08:00:01 0 000000000-000000 08:00:01 0 100000000-000000 :: : 0 111111111-111110 08:00:01 0 000000000-000001 08:00:02 0 to 1 transition of f 14 increments the time circuits 001aaj479 0.484375 - 0.500000 s 1 s
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 53 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal fig 31. stop bit functional diagram 001aaj34 2 osc 32768 hz f 0 16384 hz f 1 8192 hz f 2 4096 hz 128 hz f 8 res f 9 64 hz res f 10 lower prescaler upper prescaler res f 13 res stop 1 hz tick f 14 fig 32. stop bit release timing 001aaj34 3 0 ms - 15.625 ms 64 hz stop released
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 54 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 9. interfaces the pcf2127a has a selectable i 2 c-bus or spi-bus interface. the selection is done using the interface selection pin ifs (see ta b l e 5 6 ). table 56. interface selection input pin ifs pin connection bus interface reference ifs v ss spi-bus section 9.1 bbs i 2 c-bus section 9.2 to select the spi-bus interface, pin ifs has to be connected to pin v ss . to select the i 2 c-bus interface pin ifs has to be connected to pin bbs. a. spi-bus interface selection b. i 2 c-bus interface selection fig 33. interface selection 001aaj67 9 1 v dd bbs scl ce 20 pcf2127a 2 sdi 19 3 sdo 18 4 sda/ce 17 5 ifs 16 615 714 8 v ss 13 912 10 11 sdo sdi scl v dd v ss 001aaj68 0 1 v dd bbs scl 20 pcf2127a 2 sdi 19 3 sdo 18 4 sda/ce 17 5 ifs 16 615 714 8 v ss v ss 13 sda scl r pu r pu v dd 912 10 11
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 55 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 9.1 spi-bus interface data transfer to and from the device is made via a 3 wire spi-bus (see ta b l e 5 7 ). the data lines for input and output are split. the data input and output line can be connected together to facilitate a bi directional data bus (see figure 34 ). the spi-bus is initialized whenever the chip enable line pin sda/ce is inactive. [1] the chip enable must not be wired permanently low. 9.1.1 data transmission the chip enable signal is used to identify t he transmitted data. each data transfer is a byte, with the most signif icant bit (msb) sent first. the transmission is controlled by the active low chip enable signal sda/ce . the first byte transmitted is the comman d byte. subsequent bytes will be either data to be written or data to be read (see figure 35 ). the command byte defines the address of th e first register to be accessed and the read/write mode. the address counter will auto increm ent after every access and will reset to zero after the last valid register is accessed. the r/w bit defines if the following bytes will be read or write information. fig 34. sdi, sdo configurations table 57. serial interface symbol function description sda/ce chip enable input; active low [1] when high, the in terface is reset; input may be higher than v dd scl serial clock input when sda/ce is high, input may float; input may be higher than v dd sdi serial data input when sda/ce is high, input may float; input may be higher than v dd ; input data is sampled on the rising edge of scl sdo serial data output push-pull output; drives from v ss to v bbs ; output data is changed on the falling edge of scl 001aai56 0 sdi two wire mode sdo sdi single wire mode sdo fig 35. data transfer overview 013aaa31 1 data bus sda/ce command data data data
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 56 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal table 58. command byte definition bit symbol value description 7r/w data read or write selection 0 write data 1 read data 6 to 5 sa 01 subaddress; other codes will cause the device to ignore data transfer 4 to 0 ra 00h to 1dh register address in this example, the register seconds is set to 45 seconds and the register minutes to 10 minutes. fig 36. spi-bus write example 001aaj3 48 seconds data 45 bcd minutes data 10 bcd addr 03h r/w sa 03 xx 04 05 scl sdi sda/ce address counter b7 0 b6 0 b5 1 b4 0 b3 0 b2 0 b1 1 b0 1 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 in this example, the registers months and years are read. the pins sdi and sdo are not connected together. for this configuration, it is important that pin sdi is never left floa ting. it must always be driven either high or low. if pin sdi is left open, high i dd currents may result. fig 37. spi-bus read example 001aaj3 49 months data 11 bcd years data 06 bcd addr 08h r/w sa 08 xx 09 0a scl sdi sda/ce address counter b7 1 b6 0 b5 1 b4 0 b3 1 b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 sdo
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 57 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 9.2 i 2 c-bus interface the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines are connected to a positive supply via a pull-up re sistor. data transfer is initiated only when the bus is not busy. 9.2.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line remains stable during the high period of the clock pulse as changes in the data line at this time are interpreted as control signals (see figure 38 ). 9.2.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as the start condition s. a low-to-high transition of the data line while the clock is high, is defined as the stop condition p (see figure 39 ). remark: for the pcf2127a a repeated start is not allowed. therefore a stop has to be released before the next start. 9.2.3 system configuration a device generating a message is a transmit ter; a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves. the pcf2127a can act as a slave transmitter and a slave receiver. fig 38. bit transfer mbc62 1 data line stable; data valid change of data allowed sda scl fig 39. definition of start and stop conditions mbc62 2 sda scl p stop condition sda scl s start condition
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 58 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 9.2.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 41 . 9.2.5 i 2 c-bus protocol after a start condition a valid hardware address has to be sent to a pcf2127a device. the appropriate i 2 c-bus slave address is 1010001. the entire i 2 c-bus slave address byte is shown in table 59 . fig 40. system configuration mba60 5 master transmitter receiver slave receiver slave transmitter receiver master transmitter master transmitter receiver sda scl fig 41. acknowledgement on the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 59 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal the r/w bit defines the direction of the following si ngle or multiple byte data transfer (read is logic 1, write is logic 0). for the format and the timing of the start c ondition (s), the stop condition (p), and the acknowledge bit (a) refer to the i 2 c-bus specification ref. 13 ? um10204 ? and the characteristics table ( ta b l e 6 4 ). in the write mode a data transfer is terminated by sending either a stop condition or the start condition of the next data transfer. table 59. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 1010001r/w fig 42. bus protocol, writing to registers 001aaj71 9 s 1 0 1 slave address register address 00h to 1dh 0 to n data bytes write bit start/ stop acknowledge from pcf2127a acknowledge from pcf2127a acknowledge from pcf2127a 0 0 0 1 0 a a a p/s fig 43. bus protocol, reading from registers 001aaj72 1 s 1 0 1 slave address 0 to n data bytes data byte last data byte read bit acknowledge from pcf2127a acknowledge from master no acknowledge 0 0 0 1 1 a a s 1 0 1 slave address register address 00h to 1dh set register address read register data write bit stop acknowledge from pcf2127a acknowledge from pcf2127a 0 0 0 1 0 a a p a p
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 60 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal fig 44. bus protocol, writing to ram 001aaj72 0 s slave address 1 0 1 0 0 0 1 0 write bit a a set ram address ram write command write data to ram acknowledge from pcf2127a acknowledge from pcf2127a register address 1ah a a acknowledge from pcf2127a p/s slave address 0 to n data bytes 1 0 1 0 0 0 1 0 write bit a a acknowledge from pcf2127a acknowledge from pcf2127a acknowledge from pcf2127a register address 1ch acknowledge from pcf2127a data byte 1bh data byte 1ah a p data byte (ram address)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 61 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal fig 45. bus protocol, reading from ram 001aaj72 2 s slave address 1 0 1 0 0 0 1 0 write bit a a set ram address ram read command read data from ram acknowledge from pcf2127a acknowledge from pcf2127a register address 1ah a a acknowledge from pcf2127a p/s slave address 0 to n data bytes 1 0 1 0 0 0 1 0 write bit a a acknowledge from pcf2127a acknowledge from pcf2127a no acknowledge register address 1dh acknowledge from pcf2127a data byte 1bh data byte 1ah a p last data byte p/s slave address 1 0 1 0 0 0 1 1 read bit a a acknowledge from master acknowledge from pcf2127a data byte
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 62 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 10. internal circuitry fig 46. device diode protection diagram of pcf2127a 001aaj677 scl sdi sdo sda/ce ifs ts clkout v ss test pcf2127a pfo pfi rst int bbs v bat v dd
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 63 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 11. limiting values [1] pass level; human body model (hbm) according to ref. 7 ? jesd22-a114 ? . [2] pass level; machine model (mm), according to ref. 8 ? jesd22-a115 ? . [3] pass level; charged-device model (cdm), according to ref. 9 ? jesd22-c101 ? . [4] pass level; latch-up testing according to ref. 10 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [5] according to the nxp store and transport requirements (see ref. 12 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 60. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +4.5 v i dd supply current ? 50 +50 ma v i input voltage ? 0.5 +6.5 v i i input current ? 10 +10 ma v o output voltage ? 0.5 +6.5 v i o output current ? 10 +10 ma at pin sda/ce ? 10 +20 ma v bat battery supply voltage ? 0.5 +4.5 v p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm [1] - 3000 v mm [2] - 250 v cdm [3] - 1500 v i lu latch-up current [4] -200ma t stg storage temperature [5] ? 55 +85 c t oper operating temperature ? 40 +85 c
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 64 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 12. static characteristics table 61. static characteristics v dd = 1.8 v to 4.2 v; v ss =0v; t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage [1] 1.8 - 4.2 v v bat battery supply voltage 1.8 - 4.2 v v dd(cal) calibration supply voltage - 3.3 - v v low low voltage - 1.2 - v i dd supply current interface active spi-bus f scl = 6.5 mhz - - 800 a i 2 c-bus f scl = 400 khz - - 200 a interface inactive (f scl =0hz) clkout disabled (cof[2:0]) = 111), one power supply v dd (pwrmng[2:0] = 111), timestamp detection disabled (tsoff = 1) [2] v dd = 2.0 v - 500 - na v dd = 3.3 v - 700 1500 na v dd = 4.2 v - 800 - na clkout enabled at 32 khz (default), one power supply v dd (pwrmng[2:0] = 111), timestamp detection disabled (tsoff = 1) v dd = 2.0 v - 600 - na v dd = 3.3 v - 850 - na v dd = 4.2 v - 1050 - na clkout disabled (cof[2:0]) = 111), power management functions enabled (default), timestamp detection enabled (default) v dd = 2.0 v - 1800 - na v dd = 3.3 v - 2150 - na v dd = 4.2 v - 2350 3500 na clkout enabled at 32 khz (default); power management functions enabled (default), timestamp detection enabled (default) v dd = 2.0 v - 1900 - na v dd = 3.3 v - 2300 - na v dd = 4.2 v - 2600 - na i bat battery supply current v dd active; v bat = 3.0 v - 50 100 na power management v th(sw)bat battery switch threshold voltage -2.5-v v th(bat)low low battery threshold voltage - 2.5 - v v th(pfi) threshold voltage on pin pfi - 1.25 - v
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 65 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal [1] for reliable oscillator start-up at power-on: v dd(po)min =v dd(min) +0.3v. [2] timer source clock = 1 ? 60 hz, level of pins sda/ce , sdi and scl is v dd or v ss . [3] tested on sample basis. inputs v i input voltage ? 0.5 - v dd + 0.5 v v il low-level input voltage - - 0.25v dd v t amb = ? 20 c to +85 c; v dd >2.0v - - 0.3v dd v v ih high-level input voltage 0.7v dd --v i li input leakage current v i =v dd or v ss ? 10 +1 a c i input capacitance [3] --7pf outputs v o output voltage on pins clkout, int , rst , pfo , referring to external pull-up ? 0.5 - 5.5 v on pin sdo ? 0.5 - v bbs + 0.5 v i ol low-level output current output sink current; v ol = 0.4 v on pin sda/ce 317- ma on all other outputs 1.0 - - ma i oh high-level output current output source current; on pin sdo; v oh = 3.8 v; v dd = 4.2 v 1.0 - - ma i lo output leakage current v o = v dd or v ss ? 10 1 a table 61. static characteristics ?continued v dd = 1.8 v to 4.2 v; v ss =0v; t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ max unit
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 66 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 12.1 current consumption characteristics, typical typical value; v ol =0.4v. fig 47. i ol on pin sda/ce clkout disabled; pwrmng[2:0] = 111; tsoff = 1; ts input floating. fig 48. i dd as a function of temperature 001aal763 v dd (v) 1.5 4.5 3.5 2.5 14 10 18 22 i ol (ma) 6 temperature ( c) ? 40 100 80 60 020 ? 20 40 001aaj432 0.8 1.2 0.4 1.6 2.0 i dd ( a) 0 v dd = 3 v v dd = 2 v
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 67 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal a. pwrmng[2:0] = 111; tsoff = 1; t amb =25 c; ts input floating. b. pwrmng[2:0] = 000; tsoff = 0; t amb =25 c; ts input floating. fig 49. i dd as a function of v dd v dd (v) 1.8 4.2 3.4 2.6 2.2 3.8 3.0 001aaj433 0.8 1.2 0.4 1.6 2.0 i dd ( a) 0 clkout off clkout enabled at 32 khz v dd (v) 1.8 4.2 3.4 2.6 2.2 3.8 3.0 001aaj434 1.6 2.4 0.8 3.2 4.0 i dd ( a) 0 clkout off clkout enabled at 32 khz
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 68 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 12.2 frequency characteristics [1] 1 ppm corresponds to a time deviation of 0.0864 seconds per day. [2] not production tested. effects of reflow solder not included (see ref. 3 ? an10857 ? ). table 62. frequency characteristics v dd = 1.8 v to 4.2 v; v ss =0v; t amb =+25 c, unless otherwise specified. symbol parameter conditions min typ max unit f o output frequency on pin clkout; v dd or v bat = 3.3 v; cof[2:0] = 000; ao[3:0] = 1000 - 32.768 - khz f/f frequency stability v dd or v bat = 3.3 v t amb = ? 15 c to +60 c [1] - 3 5ppm t amb = ? 25 cto ? 15 c and t amb =+60 cto+65 c [1] - 5 10 ppm f xtal /f xtal relative crystal frequency vari ation crystal aging, first year; v dd or v bat = 3.3 v [2] -- 3ppm f/ v frequency variation with voltage on pin clkout - 1- ppm/v (1) temperature compensated frequency. (2) uncompensated typical tuni ng-fork crystal frequency. fig 50. characteristic of frequency with respect to temperature temperature ( c) ? 40 100 60 080 40 ? 20 20 001aaj650 ? 40 0 40 frequency stability (ppm) ? 80 10 ppm 5 ppm 10 ppm (1) (2)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 69 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 13. dynamic characteristics 13.1 spi-bus timi ng characteristics [1] no load value; bus will be held up by bus capacitance; use rc time constant with application values. table 63. spi-bus characteristics v dd = 1.8 v to 4.2v; v ss =0v; t amb = ? 40 c to +85 c, unless otherwise specified. all timing values are valid within the operating supply voltage at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter conditions v dd =1.8v v dd =4.2v unit min max min max pin scl f clk(scl) scl clock frequency register read/write access - 2.0 - 6.5 mhz ram write access - 2.0 - 6.5 mhz ram read access - 1.11 - 6.25 mhz t scl scl time register read/write access 800 - 140 - ns ram write access 800 - 140 - ns ram read access 900 - 160 - ns t clk(h) clock high time register read/write access 100 - 70 - ns ram write access 100 - 70 - ns ram read access 450 - 80 - ns t clk(l) clock low time register read/write access 400 - 70 - ns ram write access 400 - 70 - ns ram read access 450 - 80 - ns t r rise time for scl signal - 100 - 30 ns t f fall time for scl signal - 100 - 30 ns pin sda/ce t su(ce_n) ce_n set-up time 60 - 30 - ns t h(ce_n) ce_n hold time 40 - 25 - ns t rec(ce_n) ce_n recovery time 100 - 30 - ns t w(ce_n) ce_n pulse width - 0.99 - 0.99 s pin sdi t su set-up time set-up time for sdi data 70 - 20 - ns t h hold time hold time for sdi data 70 - 20 - ns pin sdo t d(r)sdo sdo read delay time c l = 50 pf register read access - 225 - 55 ns ram read access - 410 - 55 ns t dis(sdo) sdo disable time [1] - 90 - 25 ns t t(sdi-sdo) transition time from sdi to sdo to avoid bus conflict 0 - 0 - ns
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 70 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal fig 51. spi-bus timing 013aaa152 r/w sa2 ra0 b7 b6 b0 b7 b6 b0 b0 b6 b7 sdi sdo sdo high-z high-z sdi scl ce write read t w(ce_n) 80% 20% t clk(l) t f t h(ce_n) t rec(ce_n) t dis(sdo) t d(r)sdo t r t h t su t clk(h) t su(ce_n) t clk(scl) t t(sdi-sdo)
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 71 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 13.2 i 2 c interface timing characteristics [1] the minimum scl clock fr equency is limited by the bus time-out feature which resets the serial bus interface if either the sda or scl is held low for a minimum of 25 ms. the bus time-out feature must be disabled for dc operation. [2] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the undefined region of the scl?s falling edge. [3] c b is the total capacitance of one bus line in pf. [4] the maximum t f for the sda and scl bus lines is 300 ns. the maximum fall time for the sda output stage, t f is 250 ns. this allows seri es protection resistors to be connected between the sda/ce pin, the scl pin, and the sda/scl bus lines without exceeding the maximum t f . [5] t vd;ack is the time of the acknowledgement signal from scl low to sda (out) low. [6] t vd;dat is the minimum time for valid sda (out) data following scl low. [7] input filters on the sda and scl inputs suppress noise spikes of less than 50 ns. table 64. i 2 c-bus characteristics all timing characteristics are valid within the op erating supply voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of v ss to v dd (see figure 52 ). symbol parameter standard mode fast-mode (fm) unit min max min max pin scl f scl scl clock frequency [1] 0 100 0 400 khz t low low period of the scl clock 4.7 - 1.3 - s t high high period of the scl clock 4.0 - 0.6 - s pin sda/ce t su;dat data set-up time 250 - 100 - ns t hd;dat data hold time 0 - 0 - ns pins scl and sda/ce t buf bus free time between a stop and start condition 4.7 - 1.3 - s t su;sto set-up time for stop condition 4.0 - 0.6 - s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - s t r rise time of both sda and scl signals [2] [3] [4] - 1000 20 + 0.1c b 300 ns t f fall time of both sda and scl signals [2] [3] [4] - 300 20 + 0.1c b 300 ns t vd;ack data valid acknowledge time [5] 0.1 3.45 0.1 0.9 s t vd;dat data valid time [6] 300 - 75 - ns t sp pulse width of spikes that must be suppressed by the input filter [7] - 50 - 50 ns
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 72 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 14. application information for information about application configuration see ref. 3 ? an10857 ? . fig 52. i 2 c-bus timing diagram; rise and fall times refer to 30 % and 70 % protocol scl sda mbd82 0 bit 0 lsb (r/w) start condition (s) bit 7 msb (a7) bit 6 (a6) acknowledge (a) stop condition (p) t su;sta t hd;sta t su;dat t hd;dat t vd;dat t su;sto t low t high 1 / f scl t buf t r t f
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 73 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 15. package outline fig 53. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x a a 1 a 2 h e l p q e c l v m a (a ) 3 a s o20: plastic small outline package; 20 leads; body width 7.5 mm sot163 -1 99-12-27 03-02-19
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 74 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 16. soldering for information about soldering see ref. 3 ? an10857 ? . 17. abbreviations table 65. abbreviations acronym description am ante meridiem bcd binary coded decimal cdm charged device model cmos complementary metal-oxide semiconductor dc direct current gps global positioning system hbm human body model i 2 c inter-integrated circuit ic integrated circuit lsb least significant bit mcu microcontroller unit mm machine model msb most significant bit pm post meridiem por power-on reset poro power-on reset override ppm parts per million ram random access memory rc resistance-capacitance rtc real time clock scl serial clock line sda serial data line spi serial peripheral interface sram static random access memory tcxo temperature compensated xtal oscillator xtal crystal
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 75 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 18. references [1] an10365 ? surface mount reflow soldering description [2] an10853 ? handling precautions of esd sensitive devices [3] an10857 ? application and soldering information for pcf2127a and pcf2129a tcxo rtc [4] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [5] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [6] ipc/jedec j-std-020d ? moisture/reflow sensitiv ity classification for nonhermetic solid state surface mount devices [7] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [8] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [9] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [10] jesd78 ? ic latch-up test [11] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [12] nx3-00092 ? nxp store and transport requirements [13] um10204 ? i 2 c-bus specification and user manual
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 76 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 19. revision history table 66. revision history document id release date data sheet status change notice supersedes pcf2127a_2 20100507 product data sheet - pcf2127a_1 modifications: ? the format of this data sheet has been r edesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? adjusted i 2 c-bus specification pcf2127a_1 20100121 product data sheet - -
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 77 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 78 of 80 nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pcf2127a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 7 may 2010 79 of 80 continued >> nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 register overview . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.1 register control_1 . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 register control_2 . . . . . . . . . . . . . . . . . . . . . 10 8.2.3 register control_3 . . . . . . . . . . . . . . . . . . . . . 11 8.3 register clkout_ctl . . . . . . . . . . . . . . . . . . . 12 8.3.1 temperature compensated crystal oscillator . 12 8.3.1.1 temperature measurement . . . . . . . . . . . . . . 12 8.3.2 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.4 register aging_offset . . . . . . . . . . . . . . . . . . . 14 8.4.1 crystal aging correction . . . . . . . . . . . . . . . . . 14 8.5 general purpose 512 bytes static ram . . . . . 15 8.5.1 register ram_addr_msb . . . . . . . . . . . . . . . 15 8.5.2 register ram_addr_lsb . . . . . . . . . . . . . . . . 15 8.5.3 register ram_wrt_cmd . . . . . . . . . . . . . . . . . 15 8.5.4 register ram_rd_cmd . . . . . . . . . . . . . . . . . . 15 8.5.5 operation examples . . . . . . . . . . . . . . . . . . . . 16 8.5.5.1 writing to the ram . . . . . . . . . . . . . . . . . . . . . 16 8.5.5.2 reading from the ram . . . . . . . . . . . . . . . . . . 16 8.6 power management functions . . . . . . . . . . . . 17 8.6.1 battery switch-over function . . . . . . . . . . . . . . 18 8.6.1.1 standard mode . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6.1.2 direct switching mode . . . . . . . . . . . . . . . . . . 19 8.6.1.3 battery switch-over disabled: only one power supply (v dd ) . . . . . . . . . . . . . . . . . 20 8.6.1.4 battery switch-over architecture . . . . . . . . . . . 20 8.6.2 battery backup supply . . . . . . . . . . . . . . . . . . 20 8.6.3 battery low detection function. . . . . . . . . . . . . 21 8.6.4 extra power fail detection function . . . . . . . . . 22 8.6.4.1 extra power fail de tection when the battery switch over function is enabled. . . . . . . . . . . . 23 8.6.4.2 extra power fail de tection when the battery switch-over function is disabled . . . . . . . . . . . 24 8.7 oscillator stop detection function . . . . . . . . . . 25 8.8 reset function . . . . . . . . . . . . . . . . . . . . . . . . 26 8.8.1 power-on reset (por) . . . . . . . . . . . . . . . . . 26 8.8.2 power-on reset override (poro) . . . . . . . . 26 8.9 time and date function. . . . . . . . . . . . . . . . . . 28 8.9.1 register seconds. . . . . . . . . . . . . . . . . . . . . . 28 8.9.2 register minutes . . . . . . . . . . . . . . . . . . . . . . 28 8.9.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9.4 register days . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9.5 register weekdays . . . . . . . . . . . . . . . . . . . . 29 8.9.6 register months. . . . . . . . . . . . . . . . . . . . . . . 30 8.9.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 30 8.9.8 setting and reading the time . . . . . . . . . . . . . 30 8.10 alarm function . . . . . . . . . . . . . . . . . . . . . . . . 32 8.10.1 register second_alarm . . . . . . . . . . . . . . . . . 32 8.10.2 register minute_alarm. . . . . . . . . . . . . . . . . . 33 8.10.3 register hour_alarm . . . . . . . . . . . . . . . . . . . 33 8.10.4 register day_alarm . . . . . . . . . . . . . . . . . . . . 33 8.10.5 register weekday_alarm. . . . . . . . . . . . . . . . 34 8.10.6 alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.11 timer functions. . . . . . . . . . . . . . . . . . . . . . . . 35 8.11.1 register watchdg_tim_ctl . . . . . . . . . . . . . . . 35 8.11.2 register watchdg_tim_val . . . . . . . . . . . . . . . 36 8.11.3 watchdog timer function . . . . . . . . . . . . . . . . 36 8.11.4 countdown timer function . . . . . . . . . . . . . . . 38 8.11.5 pre-defined timers: second and minute interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.11.6 clearing flags . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.12 timestamp function . . . . . . . . . . . . . . . . . . . . 41 8.12.1 timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 41 8.12.2 time stamp mode . . . . . . . . . . . . . . . . . . . . . 42 8.12.3 timestamp registers. . . . . . . . . . . . . . . . . . . . 42 8.12.3.1 register timestp_ctl . . . . . . . . . . . . . . . . . . . 42 8.12.3.2 register sec_timestp. . . . . . . . . . . . . . . . . . . 42 8.12.3.3 register min_timestp . . . . . . . . . . . . . . . . . . . 42 8.12.3.4 register hour_timestp . . . . . . . . . . . . . . . . . . 43 8.12.3.5 register day_timestp. . . . . . . . . . . . . . . . . . . 43 8.12.3.6 register mon_timestp . . . . . . . . . . . . . . . . . . 43 8.12.3.7 register year_timestp . . . . . . . . . . . . . . . . . . 43 8.12.4 dependency between battery switch-over and timestamp . . . . . . . . . . . . . . . . . . . . . . . . 44 8.13 interrupt output, int . . . . . . . . . . . . . . . . . . . . 45 8.13.1 minute and second interrupts. . . . . . . . . . . . . 46 8.13.2 countdown timer interrupts . . . . . . . . . . . . . . 47 8.13.3 int pulse shortening . . . . . . . . . . . . . . . . . . . 48 8.13.4 watchdog timer interrupts . . . . . . . . . . . . . . . 49 8.13.5 alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 49 8.13.6 timestamp interrupts . . . . . . . . . . . . . . . . . . . 50 8.13.7 battery switch-over interrupts . . . . . . . . . . . . 50 8.13.8 battery low detection interrupts . . . . . . . . . . . 50 8.14 external clock test mode . . . . . . . . . . . . . . . . 51 8.15 stop bit function . . . . . . . . . . . . . . . . . . . . . . 52
nxp semiconductors pcf2127a integrated rtc, tcxo and quartz crystal ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 7 may 2010 document identifier: pcf2127a_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 9 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 spi-bus interface . . . . . . . . . . . . . . . . . . . . . . 55 9.1.1 data transmission . . . . . . . . . . . . . . . . . . . . . . 55 9.2 i 2 c-bus interface. . . . . . . . . . . . . . . . . . . . . . . 57 9.2.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.2 start and stop conditions . . . . . . . . . . . . . 57 9.2.3 system configuration . . . . . . . . . . . . . . . . . . . 57 9.2.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 58 10 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 62 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 63 12 static characteristics. . . . . . . . . . . . . . . . . . . . 64 12.1 current consumption characteristics, typical . 66 12.2 frequency characteristics. . . . . . . . . . . . . . . . 68 13 dynamic characteristics . . . . . . . . . . . . . . . . . 69 13.1 spi-bus timing characteristics . . . . . . . . . . . . 69 13.2 i 2 c interface timing characteristics . . . . . . . . . 71 14 application information. . . . . . . . . . . . . . . . . . 72 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 73 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 77 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 77 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 21 contact information. . . . . . . . . . . . . . . . . . . . . 78 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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